1. Field of the Invention
The present invention relates to a semiconductor memory device including a delaying circuit such as a bit line sense enable signal generating circuit, in particular to a semiconductor memory device capable of generating a bit line sense enable signal with a constant delay time.
2. Description of Related Art
In a conventional semiconductor memory device, a bit line sense enable signal generating circuit (generating circuit) is designed to include a delaying circuit comprised of resistors, capacitors and inverters. Operation of the delaying circuit is generally affected by process changes or voltage and temperature fluctuations. Accordingly, the timing delay in the bit line sense enable signal (signal) produced by the conventional generating circuit varies based on the voltage and the temperature fluctuations and the process changes.
For example, a signal with a relatively short delay time is generated by the generating circuit when the semiconductor memory device is operated at a relatively lower temperature and/or a greater operation voltage. On the contrary, a signal with a relatively long delay time is generated when the semiconductor memory device is operated at a relatively higher temperature and/or a lower operation voltage.
Accordingly, conventional semiconductor memory devices are configured to operate in response to the longest delay time produced by the generating circuit. This kind of design allows the signal to punctually amplify data transferred by a pair of bit lines without erroneous operation even if the signal is delayed from the desired time. However, the conventional generating circuit described above forces operation speed such as the data input/output time of the semiconductor memory device to become slower because the semiconductor memory device is operated in response to the longest delay time.
A study for solving the problem of the conventional semiconductor memory device is disclosed in U.S. Pat. No. 5,465,232 issued to Ong et al. (Ong). The semiconductor memory device in Ong includes a circuit for selecting a dummy sub-word line wherein the circuit is formed at a peripheral circuit area and has the same circuit configuration as a circuit for selecting a sub-word line in the memory cell array. Accordingly, the dummy sub-word line is selected at the same time when the sub-word line in the memory cell array is selected, and then a signal is generated automatically after a predetermined delay time from when the selected sub-word line is enabled. Therefore, the signal can be generated without depending on process changes or voltage and temperature fluctuations because resistors and capacitors are not included in the circuit for generating the signal.
However, the semiconductor memory device described by Ong still has the drawback that the circuit for automatically generating the signal dominates a large layout area of a semiconductor substrate, so much so that the chip size of the semiconductor memory device should be increased. Furthermore, the circuit for automatically generating the signal has to be repeatedly tested to confirm whether the circuit satisfies desired characteristics. The testing operation consumes productive time of the semiconductor memory device, decreasing the throughput of the semiconductor memory device.